A Low-Power Circuit Technique for Dynamic CMOS Logic

Abstract

Dynamic logic style is used in high performance circuit designs because of its faster speed and lesser transistor requirement as compared to static CMOS logic style. Dynamic logic has inherent disadvantages like less noise immunity and high power consumption. In this paper we have proposed a novel circuit technique for implementing dynamic gate. The proposed circuit has very less power dissipation with almost same noise immunity compared to the recently proposed circuit techniques for dynamic logic styles to improve noise immunity. The concept is validated through extensive simulation.