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http://hdl.handle.net/2080/1385
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DC Field | Value | Language |
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dc.contributor.author | Rout, P K | - |
dc.contributor.author | Panda, B P | - |
dc.contributor.author | Acharya, D P | - |
dc.contributor.author | Panda, G | - |
dc.date.accessioned | 2011-02-07T11:17:53Z | - |
dc.date.available | 2011-02-07T11:17:53Z | - |
dc.date.issued | 2011 | - |
dc.identifier.citation | International Conference on Electronic Systems (ICES-2011), National Institute of Technology, Rourkela, 7-9th January, 2011 | en |
dc.identifier.uri | http://hdl.handle.net/2080/1385 | - |
dc.description.abstract | Phase locked loops find wide application in several modern applications mostly in advance communication and instrumentation systems. PLL being a mixed signal circuit involves design challenge at high frequency. This work analyses the design of a mixed signal phase locked loop for faster phase and frequency locking. The PLL is designed in GPDK090 library of CMOS 90nm process to operate at a frequency of 1GHz with a lock time of 280.6ns. This PLL circuit is observed to consume a power of 11.9mW from a 1.8-V DC supply. | en |
dc.format.extent | 469966 bytes | - |
dc.format.mimetype | application/pdf | - |
dc.language.iso | en | - |
dc.subject | Phase frequency detector (PFD), | en |
dc.subject | loop filter, | en |
dc.subject | voltage controlled oscillator (VCO), | en |
dc.subject | phase-locked loops (PLLs). | en |
dc.title | Analysis and Design of a 1GHz PLL for Fast Phase and Frequency Acquisition | en |
dc.type | Article | en |
Appears in Collections: | Conference Papers |
Files in This Item:
File | Description | Size | Format | |
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Analysis_and_Design_of_a_1GHz_PLL.pdf | 458.95 kB | Adobe PDF | View/Open |
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