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Results 1-6 of 6 (Search time: 0.001 seconds).
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Item hits:
Issue Date
Title
Author(s)
Mar-2013
Low Latency VLSI Architecture of S-box for AES Encryption
Kumar, S
;
Sharma, V K
;
Mahapatra, K K
Apr-2013
An Improved VLSI Architecture of S-box for AES Encryption
Kumar, S
;
Sharma, V K
;
Mahapatra, K K
Jan-2015
A Novel On-Chip Self-Testing Signature Register for Low Cost Manufacturing Test
Lodha, K R
;
Kumar, S
;
Mahapatra, K K
Jun-2015
A Novel ROPUF for Hardware Security
Sahoo, S R
;
Kumar, S
;
Mahapatra, K K
Nov-2015
A Novel Regenerative and Anti-Lock Braking technique for Electric Vehicles
Maliye, S
;
Kumar, S
;
Swain, A
;
Mahapatra, K K
Dec-2015
Modified Configurable RO PUF with Improved Security Metrics
Sahoo, S R
;
Kumar, S
;
Mahapatra, K K
Discover
Author
2
Sahoo, S R
2
Sharma, V K
1
Lodha, K R
1
Maliye, S
1
Swain, A
Subject
2
S-box
1
AES
1
AES encryption
1
Anti-lock
1
ATE memory
1
buck-boost
1
Challenge Response Pair (CRP)
1
ChallengeResponse pair (CRP)
1
Composite Field Arithmetic
1
Composite field arithmetic
.
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Date issued
4
2015
2
2013