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Issue DateTitleAuthor(s)
Sep-20102-D Separable Discrete Hartley Transform Architecture for Efficient FPGA ResourceSharma, V K; Agrawal, R; Pati, U C; Mahapatra, K K
Dec-2010An Study of Removal of Subjective Redundancy in JPEG for Low Cost, Low Power, Computation efficient Circuit Design and High Compression ImageSharma, V K; Pati, U C; Mahapatra, K K
Jan-2011A Simple VLSI Architecture for Computation of 2-D DCT, Quantization and Zig-zag ordering for JPEGSharma, V K; Pati, U C; Mahapatra, K K
Feb-2011An Efficient Distributed Arithmetic based VLSI Architecture for DCTSharma, V K; Mahapatra, K K; Pati, U C

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